Hardware-Accelerated Dual-Split Trees
| dc.contributor.author | Lin, Daqi | en_US |
| dc.contributor.author | Vasiou, Elena | en_US |
| dc.contributor.author | Yuksel, Cem | en_US |
| dc.contributor.author | Kopta, Daniel | en_US |
| dc.contributor.author | Brunvand, Erik | en_US |
| dc.contributor.editor | Yuksel, Cem and Membarth, Richard and Zordan, Victor | en_US |
| dc.date.accessioned | 2020-10-30T18:18:29Z | |
| dc.date.available | 2020-10-30T18:18:29Z | |
| dc.date.issued | 2020 | |
| dc.description.abstract | Bounding volume hierarchies (BVH) are the most widely used acceleration structures for ray tracing due to their high construction and traversal performance. However, the bounding planes shared between parent and children bounding boxes is an inherent storage redundancy that limits further improvement in performance due to the memory cost of reading these redundant planes. Dual-split trees can create identical space partitioning as BVHs, but in a compact form using less memory by eliminating the redundancies of the BVH structure representation. This reduction in memory storage and data movement translates to faster ray traversal and better energy efficiency. Yet, the performance benefits of dual-split trees are undermined by the processing required to extract the necessary information from their compact representation. This involves bit manipulations and branching instructions which are inefficient in software. We introduce hardware acceleration for dual-split trees and show that the performance advantages over BVHs are emphasized in a hardware ray tracing context that can take advantage of such acceleration.We provide details on how the operations needed for decoding dual-split tree nodes can be implemented in hardware and present experiments in a number of scenes with different sizes using path tracing. In our experiments, we have observed up to 31% reduction in render time and 38% energy saving using dual-split trees as compared to binary BVHs representing identical space partitioning. | en_US |
| dc.description.number | 2 | |
| dc.description.sectionheaders | Hardware Architectures and Space Partitioning | |
| dc.description.seriesinformation | Proceedings of the ACM on Computer Graphics and Interactive Techniques | |
| dc.description.volume | 3 | |
| dc.identifier.doi | 10.1145/3406185 | |
| dc.identifier.issn | 2577-6193 | |
| dc.identifier.uri | https://doi.org/10.1145/3406185 | |
| dc.identifier.uri | https://diglib.eg.org:443/handle/10.1145/3406185 | |
| dc.publisher | ACM | en_US |
| dc.subject | Computing methodologies | |
| dc.subject | Ray tracing | |
| dc.subject | Graphics processors | |
| dc.subject | Computer systems organization | |
| dc.subject | Parallel architectures. | |
| dc.subject | acceleration structures | |
| dc.title | Hardware-Accelerated Dual-Split Trees | en_US |