Two-level Pipelining of Systolic Array Graphics Engines

Jayasinghe, J. A. K. S.; Herrmann, O. E.

Two-level Pipelining of Systolic Array Graphics Engines

Files

133-148.pdf (832.97 KB)

Date

1989

Authors

Jayasinghe, J. A. K. S.
Herrmann, O. E.

Publisher

The Eurographics Association

Abstract

In a systolic array, the maximum operating speed is determined by the most complex operation performed. In a systolic army graphics engine, capable of generating high quality images, one has to perform complex operations at a very high speed. We propose to use pipelined functional units in systolic army graphics engines as they can perform complex operations at high speeds. Due to time-varying discontinuities of operations performed by systolic army graphics engines, introduction of pipelined functional units is a complex problem. In this paper we present a methodology which solves this problem by a graph theoretic approach. Furthermore, we characterize the architectures which can be improved by pipelined functional units. Categories and Subject Descriptors: B.7.1 [Integrated Circuits}: Types and Design Styles VLSI C.l.1 [Single Data Stream Architectures}: Pipeline Processors C.S [Special-purpose and Application Based Systems}: Real-time Systems 1.3.1 [Computer Graphics]: Hardware Architecture - Raster Display Devices 1.3.7 [Computer Graphics]: Three-dimensional Graphics and Realism Color, Shading, Shadowing and Texture

        @inproceedings{:10.2312/EGGH/EGGH89/133-148
,
booktitle = {Eurographics Workshop on Graphics Hardware
},
editor = {Richard Grimsdale and Wolfgang Strasser
},
title = {{Two-level Pipelining of Systolic Array Graphics Engines
}},
author = {Jayasinghe, J. A. K. S. and 
Herrmann, O. E.
},
year = {1989
},
publisher = {The Eurographics Association
},
ISSN = {1727-3471
},
ISBN = {ISBN 3-540-53473-3
},
DOI = {/10.2312/EGGH/EGGH89/133-148
}
}